Designing an integrated circuit is a complex process in which a functional and/or operational specification for the integrated circuit is transformed in several operations into a physical integrated circuit layout which exactly describes where on a silicon wafer which materials may be implanted, deposited or removed to manufacture the integrated circuit. Using a hierarchical design style is common practice in the field of designing a large scale integrated circuit system. Separate functional blocks are designed once and they are instantiated one or more times in a hierarchical design description. In general, the term IP block is used for such a separate functional block. For example, the hierarchical top level of the hierarchical integrated circuit design may be referred to as ‘the whole design’ and at the top level several separately designed/described functional blocks are instantiated and connected to each other. On their turn, the instantiated functional blocks may also instantiate other functional blocks and provide connections between the other functional blocks and circuitry defined in the instantiated function blocks.
In order to be able to meet the functional and/or operational specification, several timing requirements are imposed on the integrated circuit design. For example, when the integrated circuit is designed to operate at a specific clock frequency, signals have to travel through the integrated circuit at a minimum speed and they may also not travel too fast to prevent that signals arrive a clock cycle too early at the specific node of the integrated circuit. The timing requirements are specified for timing paths. A timing path represents an electrical path through which a specific signal travels from one node to another node in the integrated circuit. Timing analysis tools are able to detect whether the timing paths fulfill under a set of operational conditions the timing requirements. When a timing violation of the timing requirements of a specific timing path is found, these tools at least report the violations. Automatic optimization tools may be used to adapt the design of the integrated circuit design such that, as much as possible, timing violations are solved. For example, automatic optimization tools are able to speed up certain parts of the integrated circuit design. Alternatively, or in addition, the automatic optimization tools are able to slow down certain parts of the integrated circuit design such that specific timing paths better meet their requirements. Speeding up and slow down certain parts of the integrated circuit design may, for example, result in changing sizes of gates and/or insertion of buffers.
In hierarchical integrated circuit designs a specific IP block with an output pin may be instantiated several times. At the different instances of the specific IP block an instance of the output pin may be a node on differing timing paths. It might be that at least two of the different timing paths through the instance(s) of the output pin do not meet the timing requirements imposed on the at least two different timing paths. It might also be that a solution for the timing requirement violations has to be found inside the specific IP block. However, when a solution to solve the timing requirement violations is contradictory because the timing requirements are contradictory, finding a solution inside the specific IP block may be impossible. Contradictory may refer to, for example, a solution which requires speeding up and slowing down the circuitry that provides the signal to the output pin. A well-known way of solving such a conflict is that the hierarchy of the integrated circuit design is completely, or partially, removed by flattening at least one of the instances of this IP block into the higher level design IP block. Another well-known way of solving such a conflict is that the IP block is duplicated under another name and one of the instances is replaced by the duplicated IP block, thereby creating two IP blocks that are (in so far it concerns the violated timing requirements) independent. Both solutions increase the amount of data used to describe the integrated circuit design and thereby increase design effort and design complexity.
Published U.S. Pat. No. 8,015,532B2 discloses a timing-driven cloning method. In the method of the cited US patent a gate is cloned, i.e., a layout portion that represents a logical function is cloned. In the context of a hierarchical integrated circuit design, this would result in either flattening a part of the integrated circuit design or cloning the IP block that represents the specific gate.